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NCP5612
VBandGap
LED Return
Pin 2 & 3
600 mV
R1
I REF
Pin 4
GND
GND
Note: the I REF pin must never be biased by an external voltage.
Figure 5. Basic Reference Current Source
Load Connection
The NCP5612 is capable to drive the two LED
simultaneously, as depicted (see Figure 1), but the load can
be arranged to accommodate one or two LED if necessary
NCP5612
7
in the application (see Figure 6). In this case, the two
current mirrors can be connected in parallel to drive a
single powerful LED, thus yielding 60 mA current
capability in a single LED.
NCP5612
7
LWY87S
D1
LWY87S
LWY87S
D1
C4
1 m F/6.3 V
D2
C4
1 m F/6.3 V
2
3
GND
2
3
GND
Figure 6. Typical Single and Double LED Connections
Finally, an external network can be connected across V out
and ground, but the current through such network will not
be regulated by the NCP5612 chip (see Figure 7). On top
of that, the total current out of the V out pin shall be limited
to 60 mA.
C4
Single Wire Serial Link Protocol
The proposed S?WIRE uses a pulse count technique
already existing in the data exchange systems. The protocol
supports broken transmission, assuming the hold time is
shorter than the maximum 200 m s typical specified in the
data sheet. The S?WIRE details are provided in the
AND8264 application note.
NCP5612
7
GND
1uF/6.3V
Based on the two examples provided in Figure 8, the
CNTL pin supports two digital level:
CNTL = Low 3 the system is shut?off and no current
D1
LWY87S
D3
LWY87S
flow in either LED1 or LED2.
CNTL = High 3 the system is active and the two LED
20 mA
2
LWY87S
20 mA
D2
5mA
R1
LWY87S
5mA
D4
R2
are powered according to the selected sequence.
There is no time delay associated with the Low state and
the LED are switched Off when the CNTL signal drops to
Low. To program a new LED configuration, one shall send
3
220R
GND
220R
the number of pulses on the CNTL pin according to the true
table:
? The internal counter is reset to zero on the first
negative going transient present on the CNTL pin
Figure 7. Extra Load Connected to V out
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